1. Field of Invention
This invention relates to processing of semiconductor devices and in particular double side wall spacers for lightly doped drain (LDD) and self aligned contact (SAC) definition.
2. Description of Related Art
The self aligned contact (SAC) is a powerful method used in semiconductor manufacturing to reduce chip size by shortening the separation of contact to polysilicon. This is especially true in memory products. The space used for lightly doped drain (LDD) limits the smallest size possible with SAC. Creation of a double spacer helps alleviate the conflict between LDD and SAC requirements.
In U.S. Pat. No. 5,494,838 (Chang et al.) a floating gate is created as a side wall spacer and incorporates spacer fabrication techniques to achieve a high density nonvolatile memory cell having a split gate configuration. Referring to U.S. Pat. No. 5,468,665 (Lee et al.), a process is described in which an LDD MOSFET is formed without using a side wall spacer as an ion implantation inhibiting layer in order to produce high density semiconductor devices. In U.S. Pat. No. 5,208,472 (Su et al.) a method of forming a SAC structure is described where a first side wall is used to define a LDD structure, and a second side wall is used to extend the oxide region at the gate edge and improve source/drain leakage property. In U.S. Pat. No. 4,912,061 (Nasr) a method is described for fabricating a self aligned metal oxide semiconductor device using a disposable silicon nitride spacer.
The use of spacers are important in forming SAC structures and protecting LDD near a gate which can lead to higher densities and smaller chips; however, there is a limit to which the density can be increased, particularly when the LDD and SAC requirements are in conflict. It is, therefore, the purpose of this invention to teach a means by which spacers can be used without the conflicting requirements of the lightly doped drain and the self aligned contact.